Semiconductor Hardware — March 2026
High-NA EUV Is 60% Smaller Features.
ASML Ships One Machine Per Month.
ASML is the sole commercial supplier of EUV lithography, the leading-edge tool class every advanced chipmaker depends on. Its newest High-NA EUV tools enable 8nm features vs 13nm on standard EUV, though High-NA is one path forward among several, not yet a universal requirement. Intel takes the first shipments. ASML ships 12-15 High-NA units per year.
Sources: ASML annual report 2025; Intel investor day; ASML High-NA EUV technical specifications; SEMI equipment market data.
ASML’s High-NA EUV lithography system (the EXE:5000 series) shipped its first units to Intel in 2025 and entered broader early adoption in 2026. The machine uses a numerical aperture of 0.55, up from 0.33 in standard EUV, which reduces the minimum resolvable feature size from approximately 13 nanometers to 8 nanometers. High-NA is the leading edge of a broader EUV lithography market where ASML is the sole commercial supplier; not every advanced AI accelerator requires High-NA specifically; standard EUV with multipatterning remains a viable, currently more common path for many current-generation designs. Where High-NA does matter is for the chipmakers and node generations that have specifically committed to it, like Intel’s 14A roadmap.
ASML produces 12 to 15 High-NA EUV tools per year at its Veldhoven facility, alongside a larger production run of standard EUV tools. That production rate, multiplied by the number of chipmakers who need advanced lithography to stay competitive, is one of the more binding constraints on how fast AI hardware can advance, alongside GPU packaging capacity, HBM memory supply, and advanced node fab capacity more broadly.
How High-NA Changes the Physics
Standard EUV (0.33 NA) achieves approximately 13nm half-pitch resolution and is used for TSMC N3 and Samsung 3nm nodes, with about 100 units shipped annually. High-NA EUV (0.55 NA) achieves approximately 8nm half-pitch resolution, replaces multipatterning with single-pass exposure for some layers, and targets Intel 14A and future advanced nodes at other fabs. ASML ships 12 to 15 High-NA units per year as of 2026.
The Rayleigh criterion defines the relationship: resolution equals k1 multiplied by wavelength divided by NA. Higher NA means smaller minimum features at the same 13.5nm EUV wavelength. The shift from 0.33 to 0.55 NA also eliminates several multipatterning steps on the layers where it is used, improving yield and reducing defect density for those layers.
Why This Is a Central AI Chip Bottleneck
NVIDIA’s Blackwell architecture and its successors require advancing process nodes to maintain performance-per-watt improvements that make training and inference economically viable. Those process node advances require EUV; the most advanced future nodes are expected to require High-NA EUV specifically, though the industry’s exact adoption timeline for High-NA varies by fab and by node. The supply chain runs: ASML ships EUV tools, fabs use them to produce wafers, chip designers tape out AI accelerators on those wafers, hyperscalers buy the chips. Constrain any step and the chain compresses, and EUV tooling, where ASML has no commercial competitor, is one of the tightest constraints in that chain.
Export controls have already demonstrated this constraint. The U.S. restricted ASML from shipping standard EUV machines to Chinese chipmakers in 2023. China’s most advanced domestic chips are stuck at approximately 7nm nodes achievable with DUV (deep ultraviolet) lithography, several generations behind TSMC’s current production. High-NA EUV, which ASML cannot ship to China under current controls, represents a further gap that cannot be closed by domestic Chinese tool development within the current decade.
Limitations and What the Roadmap Does Not Tell You
Production ramp is extremely slow: 12-15 High-NA units per year means each major fab gets 2-4 machines annually. Yield learning, tool calibration, and process development at the fab level take 12-18 months after installation before volume production begins.
The pellicle problem: High-NA EUV requires new pellicle technology (thin membranes that protect the mask from particles during exposure). Pellicle production for High-NA is not yet at volume, constraining throughput.
Throughput vs. standard EUV: High-NA tools currently achieve lower wafers-per-hour throughput than mature standard EUV. The economics only favor High-NA when the feature density gain outweighs the throughput penalty and cost, which depends on the specific chip design and node, meaning standard EUV remains the right choice for many designs even as High-NA rolls out.
ASML will produce more High-NA units as it scales Veldhoven capacity. The 12-15 per year figure is 2026 early production, not the steady-state. But every node transition in semiconductor history has taken longer than the announced roadmap. The AI chip supply chain’s dependence on ASML’s EUV production ramp, standard and High-NA combined, is one of several hardware constraints that matter as much as any single AI model architecture decision.
How EUV Lithography Actually Works
Extreme ultraviolet lithography prints circuit patterns using light with a 13.5-nanometer wavelength, roughly 14 times shorter than the deep ultraviolet (193nm) light used by the previous generation. Shorter wavelength means smaller features: EUV can print transistor features below 7 nanometers, enabling the chip densities that modern AI accelerators require. The physics is straightforward. The engineering is not.
Generating EUV light requires hitting tiny droplets of molten tin with a high-powered laser 50,000 times per second. Each droplet explodes into a plasma that emits EUV photons. The photons are collected by a multilayer mirror with 70% reflectivity (compared to 99%+ for DUV lenses), bounced through a series of precision mirrors, and projected through a mask onto a silicon wafer coated with photoresist. The entire process happens inside a vacuum chamber because air absorbs EUV light. Every component operates at tolerances measured in picometers.
ASML’s current EUV machines (the NXE series) cost approximately $200 million each and weigh 180 tons. They require their own building wing with dedicated power, cooling, and vibration isolation. A single machine can process 170 wafers per hour. TSMC, Samsung, and Intel operate these machines around the clock. The machines are so complex that ASML maintains permanent engineering teams at each customer site. No other company has successfully commercialized EUV lithography. Canon and Nikon never made the transition from DUV to EUV.
Why High-NA Changes the Math
The next generation, High-NA EUV (the EXE:5000 series), increases the numerical aperture from 0.33 to 0.55. It can print features 1.7 times smaller than current EUV, enabling sub-2nm chip geometries where it is adopted. The cost: roughly $350-400 million per machine. The weight: over 250 tons. The precision requirements: mirror surfaces accurate to within 0.02 nanometers, less than the width of a single atom.
ASML has delivered High-NA tools to Intel and TSMC for qualification testing. Volume production deployment is expected in 2026 to 2027, and adoption pace varies by fab based on which node generations each chosen to require it. The transition timeline matters for AI chips because NVIDIA’s future GPU architectures beyond Blackwell are expected to require High-NA EUV, or a comparably advanced successor, to achieve the transistor densities in their designs. If ASML’s production ramp delays, chip roadmaps that depend on High-NA delay with it.
The concentration risk is absolute for EUV as a category. ASML has zero commercial competitors in EUV lithography, standard or High-NA. If ASML’s factories in Veldhoven, Netherlands experienced a major disruption, there is no alternative source of EUV lithography systems anywhere in the world. The semiconductor industry’s ability to manufacture the most advanced chips depends on one company, concentrated in one country. That is a genuine single point of failure for leading-edge EUV specifically, even though chipmakers retain other paths (older nodes, DUV multipatterning) for less cutting-edge designs.
The geopolitical dimension adds another layer. ASML operates under Dutch export controls that, since October 2023, prohibit the sale of advanced lithography equipment to China. These restrictions were implemented at U.S. request and have effectively frozen Chinese semiconductor manufacturers at the DUV generation. China’s domestic alternatives (Shanghai Micro Electronics Equipment, SMEE) produce lithography systems roughly two generations behind ASML’s current EUV tools. The export controls mean ASML’s technology is not just commercially dominant. It is geopolitically contested, which adds regulatory and political risk to an already concentrated supply chain.
Sources: ASML annual report 2025; ASML EXE:5000 product specifications; Intel investor day 2025; SEMI global equipment market data; Nature Electronics lithography review. Updated 2026-08-18: distinguished ASML’s EUV monopoly (the durable, near-universal bottleneck) from High-NA EUV adoption specifically (an evolving, fab-by-fab rollout rather than a universal current requirement), and softened claims implying every AI chip generation requires High-NA today.